1. Field of the Invention
The present invention relates to a flash memory and a method for manufacturing the same. More particularly, the invention relates to an electrically writable and erasable flash memory having a floating gate electrode, and a method for manufacturing the same.
2. Description of the Related Art
Various flash memories and methods for realizing the same have been proposed, which memories allow data to be electrically written therein and erased therefrom. One of the flash memories noted quite recently uses what is called hot electron injection. Such flash memory provides a floating gate electrode in a gate insulating film located under a control gate electrode wherein a high voltage is applied to a space between a source and a drain region, and a high voltage is also applied to the control gate electrode so that a hot carrier thus generated is absorbed by an electric field in the control gate electrode and is then injected into the floating gate electrode. For example, U.S. Pat. No. 4,963,825 and Japanese unexamined Patent Application No. SHO 61-127179 disclose flash memories which are most noted as a memory having a typical structure.
FIGS. 40 through 42 are sectional views showing a structure of a so-called single memory cell of a self-aligned type which has the most simple structure among flash memories. On a practical level, such flash memories take more complicated structure, but for simplicity the flash memory will be detailed with respect to FIGS. 40 through 42. Referring to FIGS. 40 through 42, reference numeral 101 designates a P-type polysilicon layer, 102 a second gate insulating film, 103 a first gate insulating film, 104 a first polysilicon layer (floating gate electrode), 105 a third gate insulating film, 106 a second polysilicon layer (control gate electrode), 107 a source region (N.sup.+ type impurity region), 108 a drain region (N.sup.+ type impurity region), 109 a device isolation oxide film (LOCOS).
Such structure is called the self-aligned type because the floating gate electrode 104 and the control gate electrode 106 are formed in such a manner that the floating gate electrode 104 and the control gate electrode 106 are flush at the ends thereof (in self-alignment) in the longitudinal direction of the channel. It is known that the source region 107 assumes a lightly dope drain (LDD) or a double dope drain (DDD) structure so that a pressure resistance is improved in the erasing operation. FIG. 41 shows the LDD structure whereas FIG. 42 the DDD structure.
The operation principle and the feature of the memory will be briefly described hereinbelow. Data can be written into the memory cell when a high voltage is applied to the drain region 108 and the control gate electrode 106. The control gate electrode 106 absorbs a carrier generated by an avalanche breakdown in a region joining with the drain region 108 in the channel, and then the floating gate electrode accumulates the carrier thus generated. On the other hand, data is erased from the memory cell by applying a high voltage to the source region with the control gate 106 being grounded, and discharging by the Fowler-Nordheim (F-N) tunnel injection an electric load accumulated in the floating gate 104. This operation discharges an electric load through the first gate insulating film 103 thinner than the second gate insulating film 102, which is very likely to cause the F-N tunneling injection. Besides, increasing the thickness of the second gate insulating film prevents erroneous data erasure caused by a read disturb mode from the drain side during data reading.
A method for manufacturing the above described flash memories will be explained hereinbelow. At the outset, a buffer oxide film is grown to a thickness of 3000.ANG. on the P-type silicon substrate 101. Then on the buffer oxide film a 3000.ANG. thick silicon nitride film is deposited which constitutes an antioxidant film. On the silicon nitride film, a resist pattern is formed which is open to a region where a device isolation oxide film is formed to isolate a device region into an island-like configuration. The selective removal of the silicon nitride film with this pattern as a mask results in the formation of a silicon nitride film pattern which is open at a portion where the device isolation oxide film is formed. Then, after the resist pattern is removed by etching, boron ions are implanted with the silicon nitride film pattern as a mask (an injection energy; 40 KeV: a dose amount; 5.times.10.sup.13 ions/cm.sup.2) thereby forming a field dope layer. Thereafter, a silicon oxide film is grown on an exposed surface of the P-type silicon substrate to form a device isolation oxide film 109. At this step, activation and redistribution of boron atoms in the field dope layer leads to the formation of a reverse prevention layer on the lower layer of the device isolation oxide film 109.
Then, the silicon nitride film pattern is removed with dry etching. The buffer oxide film is further removed with wet etching. This is followed by thermal oxidation by which the second gate insulating film 102 is grown to a thickness of 20 nm on the exposed surface of the P-type silicon substrate. Then the resist is coated on the entire surface of the substrate so that the resist pattern is formed with the photoetching method, the pattern being open in a region which provides a gate insulating film on the side of the source region. Part of the second gate insulating film 103 is removed with hydrofluoric acid with the resist pattern as a mask. After the resist pattern is removed, the second gate insulating film 103 is formed with thermal oxidation. At this step, the second gate insulating film 102 is additionally oxidized. Hence, the second gate insulating film having a rather thick thickness is formed.
The thickness of the first gate insulating film 103 is controlled to a thickness on the order of 10 nm in the same manner as the gate insulating film of a normal flash memory. The thickness of the second gate insulating film 102 is set to 25 to 35 nm. Then, polysilicon film is grown to a thickness of 1500.ANG. on the entire surface of the substrate by chemical vapor deposition (CVD). After N-type impurities such as phosphorus or the like are introduced by thermal oxidation or ion implantation, the polysilicon film is etched with the resist pattern to form a floating gate electrode 104. After the resist pattern is removed, the surface of the floating gate electrode 104 is oxidized to form a 20 to 30 nm thick interlayer insulating film comprising an silicon oxide film. Subsequently, about 2500.ANG. thick polysilicon film is formed on the entire surface of the substrate by CVD or the like. The polysilicon film is doped with phosphorus just as the floating gate electrode 104. After that, about 1500.ANG. thick silicon oxide film is formed by, for example, the CVD.
Then the silicon oxide film and polysilicon film are etched with a mask comprising a resist film so that the silicon oxide film and the polysilicon film are consecutively patterned to form a control gate electrode 106. At this time, a portion of a floating gate electrode projecting from the lower portion of the control gate electrode 106 in the lengthwise direction of the channel is etched so that the floating gate electrode 104 and the control gate electrode 106 are formed in self-alignment. Then after the resist is removed, an oxide film is formed on the entire surface thereof, and arsenic (As) ions are implanted at a low energy using the control gate 106 and the floating gate electrode 104 as a mask so that a low concentration diffusion layer (107a and 107b) is formed in a region where a source region is formed. Then after an oxide film is formed by gas phase growth by CVD, a CVD silicon oxide film is etched back by reactive ion etching (RIE) with the result that a side wall is formed on the side of the control gate electrode 106 and the floating gate electrode 104. As ions are implanted at implantation energy of 40 KeV and in the dose amount of 5.times.10.sup.15 ions/cm.sup.2 using the control gate electrode 106, the floating gate electrode 104 and the side wall as a mask and then substrate is annealed so that a source and drain regions (107 and 108) are formed. Thereafter, an interlayer insulating film is formed in accordance with a normal process followed by providing a contact hole and performing a metallization to form a passivation film thereby completing a flash memory having the most basic structure.
In this manner thinning the film on the source side of the gate insulating film below the floating gate electrode facilitates the generation of F-N tunneling in erasing operation. Besides, since the oxide film is thick on the drain side, errors in erasure from the drain side in reading out and writing data can be prevented.
Thus, the flash memory exchanges very frequently electric loads through an extremely thin oxide film located between the channel region, the low concentration diffusion layer and the floating gate electrode. An efficiency at which carriers are exchanged largely affects the increasing of the speed at which the device can operate. In addition, it is not too much to say that the endurance and the reliability of the flash memory depends on how such thin film can be formed. However, the aforementioned conventional structure of the flash memory and conventional method for manufacturing the flash memory have the following drawbacks.
In other words, in accordance with the conventional structure of the flash memory, since the oxide film located between the channel region and the floating gate electrode and electric load associated with the ion implantation extend in an almost completely horizontal direction, there arises a problem that F-N tunneling difficult to achieve.
Besides, in the manufacturing process, a process for forming a thin oxide film below the floating gate electrode comprises a plurality of steps such as:
(1) forming a first gate insulating film, PA1 (2) coating a resist, PA1 (3) exposing and patterning the resist, PA1 (4) edging part of the first gate insulating film by using a resist pattern as a mask, PA1 (5) peeling off the resist, and PA1 (6) forming a second gate insulating film. PA1 a semiconductor substrate; PA1 a source region and a drain region formed spaced apart from each other by a definite distance on a main surface of said semiconductor substrate; PA1 a channel region provided between the source region and the drain region; PA1 a gate insulating film provided on the channel region; PA1 a floating gate electrode provided on the gate insulating film; and PA1 a control gate electrode provided with an interlayer insulating film sandwiched therebetween so that the control gate electrode at least partially laminates the floating gate electrode; PA1 the channel region and the main surface having an inclined portion and the source region being provided relatively on or below the drain region. PA1 forming a thick device isolation oxide film on a predetermined region of a main surface of a first conductive-type semiconductor substrate; PA1 removing an oxide film including part of the device isolation oxide film to form an active region having an inclined portion on the surface thereof; PA1 forming a first gate insulating film on the inclined portion of the active region and a second gate insulating film on the active region except for the inclined portion; PA1 forming a floating gate electrode on the first and the second gate insulating film; PA1 forming a third insulating film on the floating gate electrode; PA1 forming a control gate electrode so that the control gate electrode is patterned in such a manner that the control gate at least partially laminates the floating gate electrode; PA1 patterning the floating gate electrode in self-alignment with the control gate; PA1 implanting second conductive type impurity ions into the control gate electrode thereby forming a source region and a drain region.
It has been extremely difficult to form highly accurate and thin oxide thin film with good reproducibility. In addition, there exists a step at which the gate insulating film closely contacts an organic resist. In such step, it is extremely difficult to prevent contamination of the gate insulating film. Further, the oxide film is additionally oxidized after the removal of part of the first gate insulating film so that an edge stress is likely to be generated on a silicon interface in the boundary region of the first gate insulating film and the second gate insulating film. In such case, it is extremely difficult to secure a certain level of yield owing to the insulating breakdown of the oxide film before the endurance and reliability of the oxide film can attract the attention of manufacturers.
Furthermore, U.S. Pat. No. 4,964,080 and U.S. Pat. No. 5,049,515 describe flash memories having a select gate structure in which a select gate electrode is formed so that the control gate electrode closely contacts a channel region (vertical region) via an insulating film. However, these flash memories have a drawback of not being easily integrated compared with a flash memory in which the control gate electrode and the floating gate electrode are formed in self-alignment.